FIG. 1 is a schematic diagram of a voltage halving passive valley fill (PVF) circuit 100. PVF circuit 100 includes a full wave rectifier (FWR) 102 (e.g., diodes DBR1-DBR4), diodes D1-D3, fill capacitors C2, C4, C5 and resistor R1. In AC powered systems that drive DC loads or require DC supply, PVF circuit 100 can provide power to a load when the rectified AC input voltage approaches zero. PVF capacitors C2, C4, C5 are charged in series and discharged in parallel due to diodes D1-D3. During discharge, the fill capacitors provide half of the peak AC input voltage to the load.
FIG. 2 is a plot illustrating the rectified AC input voltage, which is output from FWR 102. Each cycle of the rectified AC input voltage is twice the frequency of the AC input voltage. Each cycle of the rectified AC input voltage arbitrarily starts at the beginning of time period A and ends at the end of time period A′. For discussion purposes, a cycle of the rectified AC input voltage is assumed to start at the beginning of time period B and end at the end of the next time period A.
FIG. 3 is a plot of output voltage of PVF circuit 100. PVF capacitors C2, C4, C5 charge to the peak input voltage. Because of diodes DBR1-DBR4 in FWR 102, when the rectified AC input voltage falls below one half of the peak voltage, the combined voltage on PVF capacitors C2, C4, C5, is larger than the AC input voltage and PVF capacitors C2, C4, C5 supply current to the load. The combined voltage of PVF capacitors C2, C4, C5 falls as the load draws current. Thus, the rectified AC input voltage surpasses the combined voltage on PVF capacitors C2, C4, C5 before the end of time period A.
FIG. 4 is a plot of PVF capacitor current. The current in PVF capacitors C2, C4, C5 is shown in FIG. 4. Line 402 illustrates the resistor limiting the inrush current into PVF capacitors C2, C4, C5 and line 400 illustrates a low resistor value R. During time period A, and most of time period A′, PVF capacitors C2, C4, C5 supply current to the load. During the end of time periods A, B and B′, the AC input supplies current to the load and current to charge PVF capacitors C2, C4, C5. Because PVF capacitors C2, C4, C5 are coupled in series when charging the recharge of PVF capacitors C2, C5, C5 occurs when the rectified AC input voltage is near, but prior to, the peak AC input voltage. Because PVF capacitors C2, C4, C5 are coupled in parallel during discharge, PVF capacitors C2, C4, C5 supply current to the load when the rectified AC input voltage falls below half of peak AC input voltage.
The current from the AC input is the sum of the current supplied to the load during time periods B and B′ plus the current to charge PVF capacitors C2, C4, C5. For approximately one third of the cycle of the AC input voltage (A and most of A′), the AC input sees no load and the load at the output is supplied by PVF capacitors C2, C4, C5.
FIG. 5 is a plot of actual AC current (I_ac) versus ideal AC current. For the DC current load (I_load), the actual AC current is a rather rough approximation of the ideal AC current, where “ideal” means having a higher power factor near 1.0. This is for a constant current load, meaning the output power is not constant. For a constant load power, the I_load becomes much worse (worse PF) because the current must increase near the valley to compensate for the decreasing supply voltage, as shown in FIG. 6.
FIGS. 7A and 7B are plots illustrating an input voltage waveform of PVF circuit 100 with a resistive load and resistor current limiting. One can observe from FIGS. 7A and 7B, that PVF circuit 100 is limited in its ability to provide a good power factor. The current from the AC input is zero when PVF capacitors C2, C4, C5 are conducting. Although the shape of the PVF voltage and current waveforms look better with a resistive load, there is no current drawn from the resistive load for roughly one third of the cycle and there is a current spike near the middle of the cycle to charge the PVF capacitors.
FIG. 8 is a schematic diagram of a two-stage power factor correction (PFC) converter 200. Two-stage converter 800 is a conventional solution to the power factor problem described above. First stage 802 of converter 800 includes inductor L1, diode D1, capacitor C1, resistors Ra, Rb, transistor N2 and integrated circuit IC1. Second stage 804 includes the remaining components in FIG. 8 in conjunction with IC1. The power factor correction provided by two-stage converter 800 is good but the extra inductor L1 and the associated losses and costs are not desired.